IN Brief:
- Keysight and WIN Semiconductors have introduced a joint GaN MMIC design workflow for high-frequency RF components.
- The workflow connects on-chip simulation, 3D layout verification, and off-chip evaluation-board design in one environment.
- Defence radar and satellite systems stand to benefit from reduced tapeout risk, faster validation, and better system-level RF performance.
Keysight Technologies and WIN Semiconductors have introduced a joint GaN MMIC design workflow intended to reduce fabrication risk for high-frequency RF components used in 5G, satellite payloads, Wi-Fi access points, and defence radar systems.
The workflow connects on-chip multi-domain simulation, 3D layout verification, and off-chip MMIC evaluation-board design in one environment. It uses WIN Semiconductors’ NP 120P GaN Process Design Kit inside Keysight Advanced Design System and RF Circuit Simulation Professional, giving design teams a more integrated path from circuit design to foundry submission and physical evaluation.
For defence electronics manufacturers, the target is first-pass tapeout success. A failed monolithic microwave integrated circuit tapeout can cost weeks or months, consume foundry capacity, and delay higher-level systems that depend on the component. In radar, electronic warfare, satellite communications, and high-frequency sensing, those delays can ripple from chip design into module assembly, antenna integration, qualification, and platform schedules.
GaN is central to modern RF performance because it offers high power density and efficiency at frequencies and power levels that matter for defence systems. Active electronically scanned array radars, electronic-attack systems, satellite payloads, communications terminals, and high-power RF front ends all benefit from GaN devices when design and manufacturing are controlled properly. The difficulty is that GaN MMICs are unforgiving. Layout, parasitics, thermal effects, packaging, matching networks, board transitions, and test interfaces can all degrade performance.
The Keysight-WIN workflow addresses a common RF development problem: chip and board behaviour are too often treated separately. Customers rarely commit based on a bare-die simulation alone. Performance has to be measured on a physical evaluation board that includes the MMIC, package, PCB, connectors, biasing, and test interfaces. If those off-chip elements are not co-designed, the measured result can miss specification even when the chip appears sound.
Defence radar makes that discipline especially important. A radar supplier working on transmit/receive modules or RF front ends has to manage gain, noise figure, power output, linearity, efficiency, thermal behaviour, phase stability, and reliability. The module then sits inside an array, cooling architecture, power system, and digital processing chain. A small RF design error can become expensive when multiplied across hundreds or thousands of channels.
The same pressure is visible in modern radar programmes, where gallium nitride electronics, software-defined architectures, thermal management, and repeatable high-frequency manufacturing increasingly define system performance. The Keysight-WIN work sits one layer beneath the visible radar platform, at the design workflow that helps RF components reach fabrication with fewer avoidable errors.
First-pass success is also a capacity issue. Foundry slots are valuable, and high-performance compound semiconductor production is not infinitely flexible. A failed tapeout uses engineering time and wafer capacity that could have supported production or the next design iteration. As demand grows for GaN RF devices across commercial communications, satellite systems, and defence electronics, avoiding unnecessary respins becomes a competitive advantage.
The workflow should also support smaller specialist MMIC design houses. Defence electronics supply chains often depend on niche companies with deep RF knowledge but limited room for repeated fabrication cycles. Automated verification, layout-versus-schematic checks, electromagnetic simulation, thermal analysis, and board co-design can help those companies compete, provided the tools are used with experienced engineering judgement rather than treated as a substitute for it.
The test-and-measurement connection gives the workflow additional value. Keysight’s position in electronic design automation and RF test gives engineers a route from simulation to measurement. RF teams need to correlate predicted and measured performance, then identify whether a discrepancy sits in the die, package, board, connector, fixture, or test setup. A workflow that includes the evaluation board earlier can reduce late-stage uncertainty.
Defence customers will still examine supply-chain resilience. WIN Semiconductors is a major GaAs and GaN foundry, and mature process design kits can help design houses move faster. High-performance RF components are often dual-use, however, and defence users must consider trusted supply, export controls, long-term availability, and security constraints. Design efficiency does not remove the need for supply-chain assurance.
The projected growth of GaN RF demand reinforces the production logic. Commercial networks, satellite payloads, and defence systems are all drawing from the same technology base. That demand can stimulate investment, but it can also create capacity competition. Workflows that reduce wasted fabrication cycles help the whole ecosystem use foundry resources more efficiently.
Keysight and WIN are addressing the point where many RF delays begin: the gap between chip, package, board, and test environment. Defence radar and satellite systems may appear to fail late in integration, but the root cause often sits much earlier in the design flow. Reducing that risk before the wafer run is a production advantage.
